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ltc2633 1 2633fb block diagram features description dual 12-/10-/8-bit i 2 c v out dacs with 10ppm/c reference the ltc ? 2633 is a family of dual 12-, 10-, and 8-bit voltage-output dacs with an integrated, high accuracy, low drift reference in an 8-lead tsot-23 package. it has rail-to-rail output buffers and is guaranteed monotonic. the ltc2633-l has a full-scale output of 2.5v, and o perates from a single 2.7v to 5.5v supply. the ltc2633-h has a full-scale output of 4.096v, and operates from a 4.5v to 5.5v supply. each dac can also operate with an external reference, which sets the full-scale output to the external reference voltage. these dacs communicate via a 2-wire i 2 c-compatible serial interface. the ltc2633 operates in both the standard mode (clock rate of 100khz) and the fast mode (clock rate of 400khz). the ltc2633 incorporates a power-on reset circuit. options are available for reset to zero-scale, reset to mid-scale in internal reference mode, reset to mid-scale in external reference mode, or reset with all dac outputs in a high impedance state after power-up. integral nonlinearity (ltc2633a-lz12) inl curve applications n integrated precision reference 2.5v full-scale 10ppm/c (ltc2633-l) 4.096v full-scale 10ppm/c (ltc2633-h) n maximum inl error: 1lsb (ltc2633a-12) n low noise: 0.75mv p-p 0.1hz to 200khz n guaranteed monotonic over C40c to 125c temperature range n selectable internal or external reference n 2.7v to 5.5v supply range (ltc2633-l) n low power: 0.4ma at 3v n power-on-reset to zero-scale/mid-scale/hi-z n double-buffered data latches n 8-lead thinsot? package n mobile communications n process control and industrial automation n power supply margining n portable equipment n automotive l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5396245, 5859606, 6891433, 6937178, 7414561. code 0 inl (lsb) 21 0 C1C2 1024 3072 2633 ta01 4095 2048 v cc = 3v internal ref. 2633 bd i 2 c interface i 2 c address decode power-on reset control decode logic register register register register dac b dac a v outb ref scl sda ca0 v outa v cc gnd internal reference switch v ref downloaded from: http:///
ltc2633 2 2633fb pin configuration absolute maximum ratings supply voltage (v cc ) ................................... C0.3v to 6v scl, sda ..................................................... C0.3v to 6v v outa , v outb .................... C0.3v to min(v cc + 0.3v, 6v) ca0 ................................... C0.3v to min(v cc + 0.3v, 6v) ref ................................... C0.3v to min(v cc + 0.3v, 6v) operating temperature range ltc2633c ................................................ 0c to 70c ltc2633h (note 3) ............................ C40c to 125c maximum junction temperature........................... 150c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (notes 1, 2) 12 3 4 87 6 5 top view ts8 package 8-lead plastic tsot-23 sdav cc v outb v outa sclca0 ref gnd t jmax = 150c (note 6), ja = 195c/w order information ltc2633 a c ts8 ?l z 12 #trm pbf lead free designator tape and reel tr = 2,500-piece tape and reel trm = 500-piece tape and reel resolution 12 = 12-bit 10 = 10-bit 8 = 8-bit power-on reset i = reset to mid-scale in internal reference mode x = reset to mid-scale in external reference mode (2.5v full-scale voltage, internal reference mode option only) o = reset to mid-scale in internal reference mode, dacs high z (2.5v full-scale voltage, internal reference mode option only) z = reset to zero-scale in internal reference mode full-scale voltage internal reference mode l = 2.5v h = 4.096v package type ts8 = 8-lead plastic tsot-23 temperature grade c = commercial temperature range (0c to 70c) h = automotive temperature range (C40c to 125c) electrical grade (optional) a = 1lsb maximum inl (12-bit) product part number consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc2633 3 2633fb product selection guide part number part marking** vfs with internal reference power-on reset to code power-on reference mode resolution v cc maximum inl ltc2633a-li12 ltc2633a-lx12 ltc2633a-lz12 ltc2633a-lo12* ltc2633a-hi12 ltc2633a-hz12 ltftc ltftb ltfsz lt ftv ltftf ltftd 2.5v ? (4095/4096) 2.5v ? (4095/4096) 2.5v ? (4095/4096) 2.5v ? (4095/4096) 4.096v ? (4095/4096) 4.096v ? (4095/4096) mid-scale mid-scale zero-scale high impedance mid-scale zero-scale internal external internal internal internal internal 12-bit 12-bit 12-bit 12-bit 12-bit 12-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 1lsb 1lsb 1lsb 1lsb 1lsb 1lsb ltc2633-li12 ltc2633-li10 ltc2633-li8 ltftc ltftj ltftq 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) mid-scale mid-scale mid-scale internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2633-lx12 ltc2633-lx10 ltc2633-lx8 ltftb ltfth ltftp 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) mid-scale mid-scale mid-scale external external external 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2633-lz12 ltc2633-lz10 ltc2633-lz8 ltfsz ltftg ltftn 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) zero-scale zero-scale zero-scale internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2633-lo12* ltc2633-lo10* ltc2633-lo8* lt ftv lt ftw ltftx 2.5v ? (4095/4096) 2.5v ? (1023/1024) 2.5v ? (255/256) high impedance high impedance high impedance internal internal internal 12-bit 10-bit 8-bit 2.7v to 5.5v 2.7v to 5.5v 2.7v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2633-hi12 ltc2633-hi10 ltc2633-hi8 ltftf ltftm ltfts 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) mid-scale mid-scale mid-scale internal internal internal 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb ltc2633-hz12 ltc2633-hz10 ltc2633-hz8 ltftd ltftk ltftr 4.096v ? (4095/4096) 4.096v ? (1023/1024) 4.096v ? (255/256) zero-scale zero-scale zero-scale internal internal internal 12-bit 10-bit 8-bit 4.5v to 5.5v 4.5v to 5.5v 4.5v to 5.5v 2.5lsb 1lsb 0.5lsb * contact linear technology for other hi-z options. **the temperature grade is identified by a label on the shipping container . electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. symbol parameter conditions ltc2633-8 ltc2633-10 ltc2633-12 ltc2633a-12 units min typ max min typ max min typ max min typ max dc performance resolution l 8 10 12 12 bits monotonicity v cc = 3v, internal ref. (note 4) l 8 10 12 12 bits dnl differential nonlinearity v cc = 3v, internal ref. (note 4) l 0.5 0.5 1 1 lsb inl integral nonlinearity v cc = 3v, internal ref. (note 4) l 0.05 0.5 0.2 1 1 2.5 0.5 1 lsb zse zero scale error v cc = 3v, internal ref., code = 0 l 0.5 5 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 3v, internal ref. (note 5) l 0.5 5 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coefficient v cc = 3v, internal ref. 10 10 10 10 v/c ge gain error v cc = 3v, internal ref. l 0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %fsr ltc2633-li12/-li10/-li8/-lx12/-lx10/-lx8/-lz12/-lz10/-lz8/-lo12/-lo10/-lo8/ltc2633a-li12/-lx12/-lz12/-lo12 (v fs = 2.5v) downloaded from: http:///
ltc2633 4 2633fb symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 2.5 v v psr power supply rejection v cc = 3v 10% or 5v 10% C80 db i sc short circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero scale; v out shorted to v cc full scale; v out shorted to gnd l l 27 C28 48 C48 ma ma dac i sd dac output current in high impedance mode lo options only l 0.01 0.5 a power supplyv cc positive supply voltage for specified performance l 2.7 5.5 v i cc supply current (note 7) v cc = 3v, v ref = 2.5v, external reference v cc = 3v, internal reference v cc = 5v v ref = 2.5v, external reference v cc = 5v, internal reference l l l l 0.3 0.4 0.3 0.4 0.5 0.6 0.5 0.6 ma ma ma ma i sd supply current in power-down mode (note 7) v cc = 5v l 0.5 2 a reference input input voltage range l 1 v cc v resistance l 120 160 200 k capacitance 12 pf i ref reference current, power down mode dac powered down l 0.005 5 a reference output output voltage l 1.24 1.25 1.26 v reference temperature coefficient 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short circuit current v cc = 5.5v, ref shorted to gnd 2.5 ma symbol parameter conditions ltc2633-8 ltc2633-10 ltc2633-12 ltc2633a-12 units min typ max min typ max min typ max min typ max ge tc gain temperature coefficient v cc = 3v, internal ref. (note 10) c-grade h-grade 10 10 10 10 10 10 10 10 ppm/c ppm/c load regulation internal ref., mid-scale, v cc = 3v 10%, C5ma i out 5ma v cc = 5v 10%, C10ma i out 10ma l l 0.009 0.009 0.016 0.016 0.035 0.035 0.064 0.064 0.14 0.14 0.256 0.256 0.14 0.14 0.256 0.256 lsb/ma lsb/ma r out dc output impedance internal ref., mid-scale, v cc = 3v 10%, C5ma i out 5ma v cc = 5v 10%, C10ma i out 10ma l l 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 0.09 0.09 0.156 0.156 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. ltc2633-li12/-li10/-li8/-lx12/-lx10/-lx8/-lz12/-lz10/-lz8/-lo12/-lo10/-lo8/ltc2633a-li12/-lx12/-lz12/-lo12 (v fs = 2.5v) downloaded from: http:///
ltc2633 5 2633fb electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. ltc2633-li12/-li10/-li8/-lx12/-lx10/-lx8/-lz12/-lz10/-lz8/-lo12/-lo10/-lo8/ltc2633a-li12/-lx12/-lz12/-lo12 (v fs = 2.5v) symbol parameter conditions min typ max units digital i/ov il low level input voltage (sda and scl) (note 14) l C0.5 0.3v cc v v ih high level input voltage (sda and scl) (note 11) l 0.7v cc v v il(ca0) low level input voltage on ca0 see test circuit 1 l 0.15v cc v v ih(ca0) high level input voltage on ca0 see test circuit 1 l 0.85v cc v r inh resistance from ca0 to v cc to set ca0 = v cc see test circuit 2 l 10 k r inl resistance from ca0 to gnd to set ca0 = gnd see test circuit 2 l 10 k r inf resistance from ca0 to v cc or gnd to set ca0 = float see test circuit 2 l 2 m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 12) l 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 0 50 ns i in input leakage 0.1v cc v in 0.9v cc l 1 a c in i/o pin capacitance (note 8) l 8 pf c b capacitive load for each bus line l 400 pf c ca0 external capacitive load on address pin ca0 l 10 pf ac performancet s settling time v cc = 3v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.4 4.0 4.5 s s s voltage output slew rate 1.0 v/s capacitive load driving 500 pf glitch impulse at mid-scale transition 2.8 nv?s dac-to-dac crosstalk 1 dac held at fs, 1 dac switch 0-fs 5.2 nv?s multiplying bandwidth external reference 320 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 180 160 200 180 nv/ hz nv/ hz nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference c ref = 0.1f 30 35 680 730 v p-p v p-p v p-p v p-p downloaded from: http:///
ltc2633 6 2633fb symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v. (see figure 1) (note 13) ltc2633-li12/-li10/-li8/-lx12/-lx10/-lx8/-lz12/-lz10/-lz8/-lo12/-lo10/-lo8/ltc2633a-li12/-lx12/-lz12/-lo12 (v fs = 2.5v) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specified. symbol parameter conditions ltc2633-8 ltc2633-10 ltc2633-12 ltc2633a-12 units min typ max min typ max min typ max min typ max dc performance resolution l 8 10 12 12 bits monotonicity v cc = 5v, internal ref. (note 4) l 8 10 12 12 bits dnl differential nonlinearity v cc = 5v, internal ref. (note 4) l 0.5 0.5 1 1 lsb inl integral nonlinearity v cc = 5v, internal ref. (note 4) l 0.05 0.5 0.2 1 1 2.5 0.5 1 lsb zse zero scale error v cc = 5v, internal ref., code = 0 l 0.5 5 0.5 5 0.5 5 0.5 5 mv v os offset error v cc = 5v, internal ref. (note 5) l 0.5 5 0.5 5 0.5 5 0.5 5 mv v ostc v os temperature coefficient v cc = 5v, internal ref. 10 10 10 10 v/c ge gain error v cc = 5v, internal ref. l 0.2 0.8 0.2 0.8 0.2 0.8 0.2 0.8 %fsr ge tc gain temperature coefficient v cc = 5v, internal ref. (note 10) c-grade h-grade 10 10 10 10 10 10 10 10 ppm/c ppm/c load regulation v cc = 5v 10%, internal ref. mid-scale, C10ma i out 10ma l 0.006 0.01 0.022 0.04 0.09 0.16 0.09 0.16 lsb/ma r out dc output impedance v cc = 5v 10%, internal ref. mid-scale, C10ma i out 10ma l 0.09 0.156 0.09 0.156 0.09 0.156 0.09 0.156 ltc2633-hi12/-hi10/-hi8/-hz12/-hz10/-hz8/ltc2633a-hi12/-hz12 (v fs = 4.096v) downloaded from: http:///
ltc2633 7 2633fb symbol parameter conditions min typ max units v out dac output span external reference internal reference 0 to v ref 0 to 4.096 v v psr power supply rejection v cc = 5v 10% C80 db i sc short circuit output current (note 6) sinking sourcing v fs = v cc = 5.5v zero scale; v out shorted to v cc full scale; v out shorted to gnd l l 27 C28 48 C48 ma ma power supplyv cc positive supply voltage for specified performance l 4.5 5.5 v i cc supply current (note 7) v cc = 5v, v ref =4.096v, external reference v cc = 5v, internal reference l l 0.4 0.5 0.6 0.7 ma ma i sd supply current in power-down mode (note 7) v cc = 5v l 0.5 2 a reference input input voltage range l 1 v cc v resistance l 120 160 200 k capacitance 12 pf i ref reference current, power down mode dac powered down l 0.005 5 a reference output output voltage l 2.032 2.048 2.064 v reference temperature coefficient 10 ppm/c output impedance 0.5 k capacitive load driving 10 f short circuit current v cc = 5.5v, ref shorted to gnd 4 ma digital i/ov il low level input voltage (sda and scl) (note 14) l C0.5 0.3v cc v v ih high level input voltage (sda and scl) (note 11) l 0.7v cc v v il(ca0) low level input voltage on ca0 see test circuit 1 l 0.15v cc v v ih(ca0) high level input voltage on ca0 see test circuit 1 l 0.85v cc v r inh resistance from ca0 to v cc to set ca0 = v cc see test circuit 2 l 10 k r inl resistance from ca0 to gnd to set ca0 = gnd see test circuit 2 l 10 k r inf resistance from ca0 to v cc or gnd to set ca0 = float see test circuit 2 l 2 m v ol low level output voltage sink current = 3ma l 0 0.4 v t of output fall time v o = v ih(min) to v o = v il(max) , c b = 10pf to 400pf (note 12) l 20 + 0.1c b 250 ns t sp pulse width of spikes suppressed by input filter l 0 50 ns i in input leakage 0.1v cc v in 0.9v cc l 1 a electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specified. ltc2633-hi12/-hi10/-hi8/-hz12/-hz10/-hz8/ltc2633a-hi12/-hz12 (v fs = 4.096v) downloaded from: http:///
ltc2633 8 2633fb electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specified. ltc2633-hi12/-hi10/-hi8/-hz12/-hz10/-hz8/ltc2633a-hi12/-hz12 (v fs = 4.096v) symbol parameter conditions min typ max units c in i/o pin capacitance (note 8) l 8 pf c b capacitive load for each bus line l 400 pf c ca0 external capacitive load on address pin ca0 l 10 pf ac performancet s settling time v cc = 5v (note 9) 0.39% (1lsb at 8 bits) 0.098% (1lsb at 10 bits) 0.024% (1lsb at 12 bits) 3.7 4.0 4.7 s s s voltage output slew rate 1.0 v/s capacitive load driving 500 pf glitch impulse at mid-scale transition 3.0 nv?s dac-to-dac crosstalk 1 dac held at fs, 1 dac switch 0-fs 6.7 nv?s multiplying bandwidth external reference 320 khz e n output voltage noise density at f = 1khz, external reference at f = 10khz, external reference at f = 1khz, internal reference at f = 10khz, internal reference 180 160 250 230 nv/ hz nv/ hz nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, external reference 0.1hz to 10hz, internal reference 0.1hz to 200khz, external reference 0.1hz to 200khz, internal reference c ref = 0.1f 30 40 680 750 v p-p v p-p v p-p v p-p downloaded from: http:///
ltc2633 9 2633fb symbol parameter conditions min typ max units f scl scl clock frequency l 0 400 khz t hd(sta) hold time (repeated) start condition l 0.6 s t low low period of the scl clock pin l 1.3 s t high high period of the scl clock pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t f fall time of both sda and scl signals (note 12) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v. (see figure 1) (note 13) ltc2633-hi12/-hi10/-hi8/-hz12/-hz10/-hz8/ltc2633a-hi12/-hz12 (v fs = 4.096v) note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all voltages are with respect to gnd note 3. high temperatures degrade operating lifetimes. operating lifetime is derated at temperatures greater than 105c.note 4. linearity and monotonicity are defined from code k l to code 2 n C1, where n is the resolution and k l is given by k l = 0.016 ? (2 n / v fs ), rounded to the nearest whole code. for v fs = 2.5v and n = 12, k l = 26 and linearity is defined from code 26 to code 4,095. for v fs = 4.096v and n = 12, k l = 16 and linearity is defined from code 16 to code 4,095. note 5. inferred from measurement at code 16 (ltc2633-12), code 4 (ltc2633-10) or code 1 (ltc2633-8), and at full scale. note 6. this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 7. digital inputs at 0v or v cc . note 8. guaranteed by design and not production tested. note 9. internal reference mode. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 100pf to gnd.note 10. temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range.note 11. maximum v ih = v cc(max) + 0.5v note 12. c b = capacitance of one bus line in pf note 13. all values refer to v ih = v ih(min) and v il = v il(max) levels. note 14. minimum v il exceeds the absolute maximum rating. this condition wont damage the ic, but could degrade performance. downloaded from: http:///
ltc2633 10 2633fb typical performance characteristics inl vs temperature dnl vs temperature reference output voltage vs temperature settling to 1lsb rising settling to 1lsb falling integral nonlinearity (inl) differential nonlinearity (dnl) code 0 inl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2633 g01 4095 2048 v cc = 3v code 0 dnl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2633 g02 4095 2048 v cc = 3v temperature (c) C50 inl (lsb) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2633 g03 150 0 v cc = 3v inl (pos) inl (neg) temperature (c) C50 dnl (lsb) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2633 g04 150 0 v cc = 3v dnl (pos) dnl (neg) temperature (c) C50 v ref (v) 1.2601.255 1.250 1.245 1.240 C25 125 100 75 50 25 2633 g05 150 0 v cc = 3v t a = 25c unless otherwise noted. ltc2633-l12 (internal reference, v fs = 2.5v) scl 5v/div v out 1lsb/div 2s/div 2633 g06 9th clock of 3rd data byte 1/4 scale to 3/4 scale stepv cc = 3v, v fs = 2.5v rl = 2k, cl = 100pf average of 256 events 3.6s scl 5v/div v out 1lsb/div 2s/div 2633 g07 9th clock of 3rd data byte 3/4 scale to 1/4 scale stepv cc = 3v, v fs = 2.5v rl = 2k, cl = 100pf average of 256 events 4.5s downloaded from: http:///
ltc2633 11 2633fb typical performance characteristics inl vs temperature dnl vs temperature reference output voltage vs temperature settling to 1lsb rising settling to 1lsb falling integral nonlinearity (inl) differential nonlinearity (dnl) code 0 inl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2633 g08 4095 2048 v cc = 5v code 0 dnl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2633 g09 4095 2048 v cc = 5v temperature (c) C50 inl (lsb) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2633 g10 150 0 v cc = 5v inl (pos) inl (neg) temperature (c) C50 dnl (lsb) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2633 g11 150 0 v cc = 5v dnl (pos) dnl (neg) temperature (c) C50 v ref (v) 2.0682.058 2.048 2.038 2.028 C25 125 100 75 50 25 2633 g12 150 0 v cc = 5v t a = 25c unless otherwise noted. ltc2633-h12 (internal reference, v fs = 4.096v) scl 5v/div v out 1lsb/div 2s/div 2633 g13 9th clock of 3rd data byte 1/4 scale to 3/4 scale stepv cc = 5v, v fs = 4.095v rl = 2k, cl = 100pf average of 256 events 3.8s scl 5v/div v out 1lsb/div 2s/div 2633 g14 9th clock of 3rd data byte 3/4 scale to 1/4 scalestep v cc = 5v, v fs = 4.095v rl = 2k, cl = 100pf average of 256 events 4.7s downloaded from: http:///
ltc2633 12 2633fb typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) load regulation current limiting offset error vs temperature integral nonlinearity (inl) differential nonlinearity (dnl) code 0 inl (lsb) 1.00.5 0 C0.5C1.0 256 768 2633 g15 1023 512 v cc = 3v v fs = 2.5v internal ref code 0 dnl (lsb) 1.00.5 0 C0.5C1.0 256 768 2633 g16 1023 512 v cc = 3v v fs = 2.5v internal ref code 0 inl (lsb) 0.500.25 0 C0.25C0.50 64 192 2633 g17 255 128 v cc = 3v v fs = 2.5v internal ref code 0 dnl (lsb) 0.500.25 0 C0.25C0.50 64 192 2633 g18 255 128 v cc = 3v v fs = 2.5v internal ref i out (ma) C30 ?v out (mv) 10 62 84 0 ?4 ?2?8 ?6 ?10 ?20 ?10 20 2633 g19 30 10 0 internal referencecode = mid-scale v cc = 5v (ltc2633-h) v cc = 5v (ltc2633-l) v cc = 3v (ltc2633-l) i out (ma) C30 ?v out (v) 0.200.15 0.05 0.10 0 ?0.05?0.15 ?0.10?0.20 ?20 ?10 20 2633 g20 30 10 0 internal referencecode = mid-scale v cc = 5v (ltc2633-h) v cc = 5v (ltc2633-l) v cc = 3v (ltc2633-l) temperature (c) C50 offset error (mv) 32 1 0 C1C2 C3 C25 125 100 75 50 25 2633 g21 150 0 t a = 25c unless otherwise noted. ltc2633-10 ltc2633-8 ltc2633 downloaded from: http:///
ltc2633 13 2633fb typical performance characteristics headroom at rails vs output current exiting power-down to mid-scale power-on reset to mid-scale supply current vs logic voltage exiting power-down for hi-z option large-signal response mid-scale-glitch impulse power-on reset glitch 2s/div v out 0.5v/div 2633 g22 v fs = v cc = 5v 1/4 scale to 3/4 scale 200s/div v out 10mv/div v cc 2v/div 2633 g24 ltc2633-l zero-scale i out (ma) 0 v out (v) 5.04.0 3.0 4.53.5 2.5 1.5 2.00.5 1.0 0 2 1 3 8 2633 g25 10 6 9 7 4 5 5v sourcing 5v sinking 3v (ltc2633-l) sourcing 3v (ltc2633-l) sinking t a = 25c unless otherwise noted. ltc2633 1.00.8 0.6 0.4 1.20.2 1 2 3 logic voltage (v) 4 5 0 i cc (ma) 2633 g28 v cc = 3v (ltc2633-l) sweep sda, scl between on and v cc v cc = 5v scl 5v/div v out 500mv/div 5s/div 2633 g29 9th clock of 3rd data byte ltc2633-lo, v cc = 3v dac output drivenby 1v source through 15k resistor high-impedance(power-down) mode dac output setto mid-scale scl 5v/div v outa 0.5v/div 5s/div 2633 g26 9th clock of 3rd data byte ltc2633-h v cc = 5v internal ref. dac b inpower-down mode 200s/div v cc 2v/div v out 0.5v/div 2633 g27 ltc2633-h ltc2633-l scl 5v/div v out 2mv/div 2s/div 2633 g23 9th clock of 3rd data byte ltc2633-h12, v cc = 5v 3n v?s typical ltc2633-l12, v cc = 3v 2.8n v?s typical downloaded from: http:///
ltc2633 14 2633fb typical performance characteristics gain error vs reference input 0.1hz to 10hz voltage noise dac to dac crosstalk (dynamic) gain error vs temperature multiplying bandwidth noise voltage vs frequency frequency (hz) 1k db 20 C2C6 C4C8 C12 C10C16 C14C18 100k 2633 g31 1m 10k v cc = 5v v ref(dc) = 2v v ref(ac) = 0.2v p-p code = full-scale temperature (c) C50 gain error (%fsr) 1.00.5 0 C0.5C1.0 C25 125 100 75 50 25 2633 g36 150 0 1s/div 10v/div 2632 g34 v cc = 5v, v fs = 2.5v code = mid-scaleinternal reference t a = 25c unless otherwise noted. ltc2633 reference voltage (v) 1 2.5 2 gain error (%fsr) 0.80.4 0.6 0 0.2 C0.4C0.6 C0.2C0.8 4.5 2633 g33 5.5 3.5 1.5 4 5 3 v cc = 5.5v gain error of 2 channels pin functions scl (pin 1): serial clock input pin. data is shifted into the sda pin at the rising edges of the clock. this high impedance pin requires a pull-up resistor or current source to v cc . ca0 (pin 2): chip address bit 0. tie this pin to v cc , gnd or leave it floating to select an i 2 c slave address for the part (see table 1). ref (pin 3): reference voltage input or output. when external reference mode is selected, ref is an input (1v v ref v cc ) where the voltage supplied sets the full-scale dac output voltage. when internal reference is selected, the 10ppm/c 1.25v (ltc2633-l) or 2.048v (ltc2633-h) internal reference (half full-scale) is available at the pin. this output may be bypassed to gnd with up to 10f (0.1f is recommended) and must be buffered when driving external dc load current. gnd (pin 4): ground. v outa , v outb (pins 5,6): dac analog voltage output. v cc (pin 7): supply voltage input. 2.7v v cc 5.5v (ltc2633-l) or 4.5v v cc 5.5v (ltc2633-h). bypass to gnd with a 0.1f capacitor. sda (pin 8): serial data bidirectional pin. data is shifted into the sda pin and acknowledged by the sda pin. this pin is high impedance while data is shifted in. open drain n-channel output during acknowledgement. sda requires a pull-up resistor or current source to v cc . frequency (hz) 100 1k noise voltage (nv / hz ) 500300 400100 200 0 100k 2633 g32 1m 10k v cc = 5v code = mid-scaleinternal reference ltc2633-h ltc2633-l scl 5v/div v out 2mv/div 1 dac switch 0-fs 2v/div 2s/div 2633 g35 9th clock of 3rd data byte ltc2633-h12, v cc = 5v 6.7n v?s typ downloaded from: http:///
ltc2633 15 2633fb block diagram test circuit test circuits for i 2 c digital i/o (see electrical characteristics) test circuit 1 test circuit 2 timing diagram figure 1. i 2 c timing figure 2. typical ltc2633 write transaction 2633 bd i 2 c interface i 2 c address decode power-on reset control decode logic register register register register dac b dac a v outb ref scl sda ca0 v outa v cc gnd internal reference switch v ref 2633 tc01 ca0 v ih(ca0) /v il(ca0) 100 2633 tc02 ca0 gnd r inh /r inl/ r inf v dd scl sda 2633 f01 t low t f t f t r t hd(sta) t hd(dat) s s p s t su(sta) t su(sto) t buf t r t su(dat) t hd(sta) t sp t high all voltage levels refer to v ih(min) and v il(max) levels 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda a6 a5 a4 a3 a2 a1 a0 c3 c2 c1 c0 a3 a2 a1 a0 w ack ack ack ack x x x x start slave address 1st data byte 2nd data byte 3rd data byte 2633 f02 scl downloaded from: http:///
ltc2633 16 2633fb operation the ltc2633 is a family of dual voltage output dacs in an 8-lead tsot package. each dac can operate rail-to-rail using an external reference, or with its full-scale voltage set by an integrated reference. eighteen combinations of accuracy (12-, 10-, and 8-bit), power-on reset value (zero- scale, mid-scale in internal reference mode, or mid-scale in external reference mode), dac power-down output load (high impedance or 200k), and full-scale voltage (2.5v or 4.096v) are available. the ltc2633 is controlled using a 2-wire i 2 c interface. power-on reset the ltc2633-hz/ltc2633-lz clear the output to zero-scale when power is first applied, making system initialization consistent and repeatable. for some applications, downstream circuits are active dur - ing dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2633 contains circuitry to reduce the power-on glitch: the analog output typically rises less than 10mv above zero scale during power-on. in general, the glitch amplitude decrease s as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics section. the ltc2633-hi/ltc2633-li/ltc2633-lx provide an alternative reset, setting the output to mid-scale when power is first applied. the ltc2633-li/ and ltc2633-hi power up in internal reference mode, with the output set to a mid-scale voltage of 1.25v and 2.048v respectively. the ltc2633-lx power-up in external reference mode, with the output set to mid-scale of the external reference. the ltc2633-lo powers up in internal reference mode with all the dac channels placed in the high impedance state (powered down). input and dac registers are set to the mid-scale code, and only the internal reference is powered up, causing supply current to be typically 180a upon power up. default reference mode selection is described in the reference modes section. power supply sequencingthe voltage at ref (pin 3) must be kept within the range C0.3v v ref v cc + 0.3v (see absolute maximum rat - ings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc is in transition. transfer function the digital-to-analog transfer function is: v out(ideal) = k 2 n v ref where k is the decimal equivalent of the binary dac input code, n is the resolution, and v ref is either 2.5v (ltc2633-li/ ltc2633-lx/ltc2633-lo/ltc2633-lz) or 4.096v (ltc2633-hi/ltc2633-hz) when in internal reference mode, and the voltage at ref when in external reference mode. i 2 c serial interface the ltc2633 communicates with a host using the stan - dard 2-wire i 2 c interface. the timing diagram (figures 1 and 2) show the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the value of these pull-up resistors is dependent on the power supply and can be obtained from the i 2 c specifications. for an i 2 c bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pf. the ltc2633 is a receive-only (slave) device. the master can write to the ltc2633. the ltc2633 will not acknowl - edge (nak) a read request from the master. downloaded from: http:///
ltc2633 17 2633fb operation start (s) and stop (p) conditions when the bus is not in use, both scl and sda must be high. a bus master signals the beginning of a communica - tion to a slave device by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop condition. a stop condition is generated by transitioning sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. acknowledgethe acknowledge (ack) signal is used for handshaking between the master and the slave. an ack generated by the slave lets the master know that the latest byte of informa - tion was properly received. the ack related clock pulse is generated by the master. the master releases the sda line (high) during the ack clock pulse. the slave-receiver must pull down the sda bus line during the ack clock pulse so that it remains a stable low during the high period of this clock pulse. the ltc2633 responds to a write by a master in this manner but does not acknowledge a read operation; in that case, sda is retained high during the period of the ack clock pulse. chip address the state of pin ca0 determines the slave address of the part. this pin can be set to any one of three states: v cc , gnd or float. this results in 3 selectable addresses for the part. the slave address assignments is shown in table 1. table 1. slave address map ca0 a6 a5 a4 a3 a2 a1 a0 gnd 0 0 1 0 0 0 0 float 0 0 1 0 0 0 1 v cc 0 0 1 0 0 1 0 global addr 1 1 1 0 0 1 1 in addition to the address selected by the address pin, the part also responds to a global address. this address allows a common write to all ltc2633 parts to be ac- complished using one 3-byte write transaction on the i 2 c bus. the global address, listed at the end of tables 1, is a 7-bit hardwired address not selectable by ca0. if another address is required, please consult the factory. the maximum capacitive load allowed on the address pin (ca0) is 10pf, as these pins are driven during address detection to determine if they are floating. write word protocol the master initiates communication with the ltc2633 with a start condition and a 7-bit slave address followed by the write bit (w) = 0. the ltc2633 acknowledges by pulling the sda pin low at the 9th clock if the 7-bit slave address matches the address of the part (set by ca0) or the global address. the master then transmits three bytes of data. the ltc2633 acknowledges each byte of data by pulling the sda line low at the 9th clock of each data byte transmission. after receiving three complete bytes of data, the ltc2633 executes the command specified in the 24-bit input word. if more than three data bytes are transmitted after a valid 7-bit slave address, the ltc2633 does not acknowledge the extra bytes of data (sda is high during the 9th clock). downloaded from: http:///
ltc2633 18 2633fb the format of the three data bytes is shown in figure 3. the first byte of the input word consists of the 4-bit command, followed by the 4-bit dac address. the next two bytes contain the 16-bit data word, which consists of the 12-, 10- or 8-bit input code, msb to lsb, followed by 4, 6 or 8 dont-care bits (ltc2633-12, ltc2633-10 and ltc2633-8 respectively). a typical ltc2633 write transaction is shown in figure 4. the command bit assignments (c3-c0) and address (a3- a0) assignments are shown in tables 3 and 4. the first four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register. in an update operation, the data word is copied from the input register to the dac register. once copied into the dac register, the data word becomes the active 12-, 10-, or 8-bit input code, and is converted to an analog voltage at the dac output. write to and update combines the first two commands. the update operation also powers up the dac if it had been in power-down mode. the data path and registers are shown in the block diagram. d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x d11 a0 a1 a2 a3 c0 c1 c2 c3 2nd data byte 1st data byte input word (ltc2633-12) write word protocol ltc2633 3rd data byte 2633 f03 x a a a p a w s input word slave address 1st data byte 2nd data byte 3rd data byte d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x d9 a0 a1 a2 a3 c0 c1 c2 c3 2nd data byte 1st data byte input word (ltc2633-10) 3rd data byte x d6 d5 d4 d3 d2 d1 d0 x x x x x x x d7 a0 a1 a2 a3 c0 c1 c2 c3 2nd data byte 1st data byte input word (ltc2633-8) 3rd data byte x operation figure 3. command and data input format table 3. command codes command* c3 c2 c1 c0 0 0 0 0 write to input register n 0 0 0 1 update (power-up) dac register n 0 0 1 0 write to input register n, update (power-up) all 0 0 1 1 write to and update (power-up) dac register n 0 1 0 0 power-down n 0 1 0 1 power-down chip (all dacs and reference) 0 1 1 0 select internal reference (power-up reference) 0 1 1 1 select external reference (power-down internal reference) 1 1 1 1 no operation *command codes not shown are reserved and should not be used. table 4. address codes address (n)* a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 1 1 1 1 all dacs * address codes not shown are reserved and should not be used. downloaded from: http:///
ltc2633 19 2633fb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda a6 a5 a4 a3 a2 a1 a0 a6 a5 a4 a3 a2 a1 a0 wr c3 c2 c1 c0 a3 a2 a1 a0 c3 c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x ack ack ack ack stop full-scale voltage zero-scale voltage start slave address scl 2633 f04 v out x = dont care command ms data ls data operation figure 4. typical ltc2633 input waveform?programming dac output for full scale downloaded from: http:///
ltc2633 20 2633fb reference modesfor applications where an accurate external reference is either not available, or not desirable due to limited space, the ltc2633 has a user-selectable, integrated reference. the integrated reference voltage is internally amplified by 2x to provide the full-scale dac output voltage range. the ltc2633-li/ltc2633-lx/ltc2633-lo/ltc2633-lz provides a full-scale output of 2.5v. the ltc2633-hi/ ltc2633-hz provides a full-scale output of 4.096v. the internal reference can be useful in applications where the supply voltage is poorly regulated. internal reference mode can be selected by using command 0110b, and is the power-on default for ltc2633-hz/ltc2633-lz, as well as for ltc2633-hi/ltc2633-li/ltc2633-lo. the 10ppm/c, 1.25v (ltc2633-li/ltc2633-lx/ltc2633- lo/ltc2633-lz) or 2.048v (ltc2633-hi/ltc2633-hz) internal reference is available at the ref pin. adding bypass capacitance to the ref pin will improve noise performance; 0.1f is recommended and up to 10f can be driven without oscillation. this output must be buffered when driving an external dc load current. alternatively, the dac can operate in external reference mode using command 0111b. in this mode, an input voltage supplied externally to the ref pin provides the reference (1v v ref v cc ) and the supply current is reduced. the external reference voltage supplied sets the full-scale dac output voltage. external reference mode is the power-on default for ltc2633-lx. the reference mode of ltc2633-hz/ltc2633-lz/ ltc2633-hi/ltc2633-li/ltc2633-lo (internal reference power-on default), can be changed by software command after power up. the same is true for ltc2633-lx (external reference power-on default). power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than two dac outputs are needed. when in power-down, the buffer amplifiers, bias circuits, and integrated reference circuits are disabled, and draw essentially zero current. the dac outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 200k resistors (ltc2633-li/ltc2633-lx/ ltc2633-lo/ltc2633-lz/ltc2633-hi/ltc2633-hz). for the ltc2633-lo options, the output pins are not passively pulled to ground, but are also placed in a high impedance state (open-circuited state) during power-down, typically drawing less than 0.1a. the ltc2633-lo options power- up with all dac outputs in this high impedance state. they remain that way until given a software update command. for all ltc2633 options, input- and dac-register contents are not disturbed during power-down. any channel or combination of channels can be put into power-down mode by using command 0100b in combi - nation with the appropriate dac address, (n). the supply current is reduced approximately 30% for each dac powered down. the integrated reference is automatically powered down when external reference is selected using command 0111b. in addition, all the dac channels and the integrated reference together can be put into power-down mode using power down chip command 0101b. when the integrated reference is in power-down mode, the ref pin becomes high impedance (typically > 1g). for all power-down commands the 16-bit data word is ignored. normal operation resumes after executing any command that includes a dac update, (as shown in table 1). the selected dac is powered up as its voltage output is up- dated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if less than two dacs are in a powered-down state prior to the update command, the power-up delay time is 10s. however, if both dacs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the dac amplifiers and reference buffers. in this case, the power up delay time is 12s. the power-up of the integrated refer - ence depends on the command that powered it down. if the reference is powered down using the select external reference command (0111b), then it can only be powered back up using select internal reference command (0110b). however, if the reference was powered down using power down chip command (0101b), then in addition to select operation downloaded from: http:///
ltc2633 21 2633fb figure 5. effects of rail-to-rail operation on a dac transfer curve (shown for 12 bits). (a) overall transfer function (b) effect of negative offset for codes near zero (c) effect of positive full-scale error for codes near full scale 2633 f05 input code (b) output voltage negative offset 0v 0v 2,048 0 4,095 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positivefse operation internal reference command (0110b), any command in software that powers up the dacs will also power up the integrated reference. voltage output the ltc2633s integrated rail-to-rail amplifier has guaran - teed load regulation when sourcing or sinking up to 10ma at 5v, and 5ma at 3v. load regulation is a measure of the amplifiers ability to maintain the rated voltage accuracy over a wide range of load current. the measured change in output voltage per change in forced load current is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to . the amplifiers dc output impedance is 0.1 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 50 typical channel resistance of the output devices (e.g., when sinking 1ma, the minimum output voltage is 50 ? 1ma, or 50mv). see the graph headroom at rails vs output current in the typical performance character - istics section. the amplifier is stable driving capacitive loads of up to 500pf. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog output of the dac cannot go below ground, it may limit for the lowest codes as shown in figure 5b. similarly, limiting can occur near full scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc , as shown in figure 5c. no full-scale limiting can occur if v ref is less than v cc Cfse. offset and linearity are defined and tested over the region of the dac transfer function where no output limiting can occur. downloaded from: http:///
ltc2633 22 2633fb board layout the pc board should have separate areas for the analog and digital sections of the circuit. a single, solid ground plane should be used, with analog and digital signals carefully routed over separate areas of the plane. this keeps digital signals away from sensitive analog signals and minimizes the interaction between digital ground currents and the analog section of the ground plane. the resistance from the ltc2633 gnd pin to the ground plane should be as low as possible. resistance here will add directly to the effective dc output impedance of the device (typically 0.1). note that the ltc2633 is no more susceptible to this effect than any other parts of this type; on the con - trary, it allows layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. another technique for minimizing errors is to use a sepa - rate power ground return trace on another board layer. the trace should run between the point where the power supply is connected to the board and the dac ground pin. thus the dac ground pin becomes the common point for analog ground, digital ground, and power ground. when the ltc2633 is sinking large currents, this current flows out the ground pin and directly to the power ground trace without affecting the analog ground plane voltage. it is sometimes necessary to interrupt the ground plane to confine digital ground currents to the digital portion of the plane. when doing this, make the gap in the plane only as long as it needs to be to serve its purpose and ensure that no traces cross over the gap. operation package description 1.50 C 1.75 (note 4) 2.80 bsc 0.22 C 0.36 8 plcs (note 3) datum a 0.09 C 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 C 0.90 1.00 max 0.01 C 0.10 0.20 bsc 0.30 C 0.50 ref pin one id note:1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) downloaded from: http:///
ltc2633 23 2633fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 3/11 revised part numbering. 2 to 9, 13, 16, 20, 26 b 3/11 revised title of typical application. 24 downloaded from: http:///
ltc2633 24 2633fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2011 lt 0311 rev b ? printed in usa related parts typical application voltage margining application with ltc3850 (1.2v 5%) ltc2633-lo option only part number description comments ltc2632 dual 12-/10-/8-bit, spi v out dacs with internal reference 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, 8-pin thinsot? package ltc2607/ltc2617/ ltc2627 dual 16-/14-/12-bit, i 2 c v out dacs with external reference 260a per dac, 2.7v to 5.5v supply range, rail-to-rail output, 16-lead ssop package ltc2602/ltc2612/ ltc2622 dual 16-/14-/12-bit spi v out dacs with external reference 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, 8-lead msop package ltc1662 dual 10-bit, spi v out dac with external reference 1.5a per dac, 2.7v to 5.5v supply range, rail-to-rail output, 8-lead msop package ltc2630/ltc2631 single 12-/10-/8-bit, spi/ i 2 c v out dacs with 10ppm/c reference 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, rail-to-rail output, in sc70 (ltc2630)/ thinsot (ltc2631) ltc2640 single 12-/10-/8-bit, spi v out dacs with 10ppm/c reference 180a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, in thinsot ltc2634/ltc2635 quad 12-/10-/8-bit spi/i 2 c v out dacs with 10ppm/c reference 2.5lsb inl, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, 16-pin 3mm 3mm qfn and 10-lead msop packages ltc2636/ltc2637 octal 12-/10-/8-bit, spi/i 2 c v out dacs with 10ppm/c reference 125a per dac, 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, 14-lead 4mm 3mm dfn and 16-lead msop packages ltc2654/ltc2655 quad 16-/12 bit, spi/i 2 c v out dacs with 10ppm/c max reference 4lsb inl max at 16-bits and 2mv offset error, rail-to-rail output, 20-lead 4mm 4mm qfn and 16-lead narrow ssop packages ltc2656/ltc2657 octal 16-/12 bit, spi/i 2 c v out dacs with 10ppm/c max reference 4lsb inl max at 16-bits and 2mv offset error, rail-to-rail output, 20-lead 4mm 5mm qfn and 16-lead tssop packages sw1 bg1 pgnd i th1 sense1 + mode/pllin run1 sense1 C v fb1 500khz tkss1 i lm v in intv cc pgood tg1 0.1f 1nf 0.1f 2.2k 100k 10k sgnd 10k 0.008k 2.2h ltc3850euf 2633 ta02 freq boost1 0.1f cmdsh-3 rjk0305dpbrjk0301dpb 10nf 1nf 3.32k 10k 1nf 10k 100pf 4.7f v in 6.5vto 14v v out 1.2v 5% 20k 15pf 63.4k to i 2 c bus ref v cc 3 7 64 5v 52 1 8 ca0 scl gnd sda 0.1f dac b dac a ltc2633cts8-l012 0.22f 10k 15k downloaded from: http:///

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